circuit CAD

Modular verification of timed circuits using automatic abstraction

The major barrier that prevents the application of formal verification to large designs is state explosion. This paper presents a new approach for verification of timed circuits using automatic abstraction. This approach partitions the design into …

Cell library for automatic synthesis of analog error control decoders

This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the …

Timed circuit verification using TEL structures

Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, …

POSET timing and its application to the synthesis and verification of gate-level timed circuits

This paper presents a new algorithm for timed state-space exploration, POSET timing, POSET timing improves upon geometric methods by utilizing concurrency and causality information to dramatically reduce the number of geometric regions needed to …

RAPPID: an asynchronous instruction length decoder

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID (\"Revolving Asynchronous Pentium(R) Processor Instruction Decoder\"), a prototype IA32 …

Automatic synthesis of gate-level timed circuits with choice

This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate …