This thesis presents a framework for the specification and compilation of modules in a system that uses different synchronization paradigms. These timed systems are described by using timed handshaking expansions (HSE) and a standard hardware description language, namely VHDL. Synthesizable subsets of these languages are defined to include constructs for describing timing behaviors, as well as, sequencing, concurrency, choice and looping. A new formal semantic model, timed event/level structures, is used to define the behaviors specified by the synthesizable subsets. A compiler is developed to translate the HSE and VHDL specifications to timed event/level structures. This compiler is integrated into ATACS, a synthesis tool for timed circuits. Finally we demonstrate our methodology on a practical example, an asynchronous implementation of the Maxlist algorithm.