State space reductions for scalable verification of asynchronous designs

Abstract

This paper presents several state space reductions for verifying non-trivial asynchronous designs with a compositional minimization approach. These reductions result in a reduced model that contains the exact set of observably equivalent behavior. Therefore no false counter-examples are produced at the end of verification. The experimental results show good scale-up of compositional minimization using these reductions on a number of asynchronous designs.

Publication
2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Hao Zheng
Hao Zheng
University of South Florida, Associate Professor

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