Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS


An all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s.

Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001