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A scheduling method for asynchronous bundled-data implementations
Hiroshi Saito
,
N. Jundapetch
,
Tomohiro Yoneda
,
Chris Myers
June 2005
Cite
Type
Conference paper
Publication
2005 Int. Workshop on Logic Synthesis
asynchronous circuit
Chris Myers
Department Chair / Professor
Related
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation
Automatic Derivation of Timing Constraints by Failure Analysis
Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
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