A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

Abstract

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

Publication
2008 8th International Conference on Application of Concurrency to System Design
Chris Myers
Chris Myers
Department Chair / Professor

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