A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris Myers, Takashi Nanya
June 2008
DOI

Abstract

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

Type
Conference paper
Publication
2008 8th International Conference on Application of Concurrency to System Design
asynchronous circuits asynchronous circuit network synthesis RTL model resource management scheduling algorithm signal synthesis space exploration processor scheduling circuit analysis circuit circuit synthesis clock control system informatics
Chris Myers
Chris Myers
Department Chair / Professor

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