The Case for Analog Circuit Verification

Abstract

The traditional approach to validate analog circuits is to utilize extensive SPICE-level simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulation-only based validation methodology and the potential benefits of formal verification of analog circuits.

David Walter
David Walter
Amazon (AWS S3), Senior SDE
Scott Little
Scott Little
Maxim Integrated, EDA

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