Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits

Scott Little, Alper Sen, Chris Myers
December 2007
DOI

Abstract

Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models precludes their widespread use. This paper presents an automated method to generate abstract models appropriate for system-level simulation and formal verification. This method uses simulation traces and thresholds on the design variables to generate a piecewise-linear representation of the system. This piecewise-linear representation can be converted to a Verilog-AMS model or a Labeled Hybrid Petri Net formal model. Results are presented for the model generation, simulation, and verification of a PLL phase detector circuit.

Type
Conference paper
Publication
2007 Eighth International Workshop on Microprocessor Test and Verification
hardware description language mixed analogue-digital integrated circuits verification formal verification Integrated circuit modeling mixed-signal circuit digital simulation analog/mixed-signal circuit analogue circuits automated model generation technique circuit simulation Detectors labeled hybrid Petri net formal model modeling phase locked loops piecewise linear techniques PLL phase detector circuit system-level simulation Verilog-AMS model reactive power switches petri nets phase detection capacitor circuit hardware design language
Scott Little
Scott Little
Maxim Integrated, EDA
Chris Myers
Chris Myers
Department Chair / Professor

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