Analog/mixed-signal circuit verification using models generated from simulation traces

Abstract

Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining circuit models at suitable levels of abstraction. We propose a method to automatically generate abstract models suitable for formal verification and system-level simulation from transistor-level simulation traces. This paper discusses the application of the proposed methodology to a switched capacitor integrator and PLL phase detector.

Scott Little

Maxim Integrated, EDA

David Walter

Amazon (AWS S3), Senior SDE

Kevin Jones

Lockheed Martin, Senior Cyber Applied Research Scientist

Chris Myers

Department Chair / Professor