Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
Abstract
Formal and semi-formal verification of analog/mixed-signal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the original simulation traces used to generate it plus additional behavior. Information obtained during the model generation process can also be used to refine the simulation and verification process.
Type
Publication
Automated Technology for Verification and Analysis
Scott Little
Maxim Integrated, EDA
David Walter
Amazon (AWS S3), Senior SDE
Kevin Jones
Lockheed Martin, Senior Cyber Applied Research Scientist
