LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits

Andrew N. Fisher, Satish Batchu, Kevin Jones, Dhanashree Kulkarni, Scott Little, David Walter, Chris J. Myers
August 2014
DOI

Abstract

The increasing integration of analog/mixed-signal (AMS) circuits into system designs has further complicated an already difficult verification problem. Recently, formal verification, which has been successful in the purely digital domain, has made some in-roads in the AMS domain. This paper describes one such formal verification tool for AMS circuits, LEMA. In particular, LEMA is capable of generating a formal model from simulation traces that, when coupled with a formal property provided in our new property language, can be model checked with one of three model checkers within LEMA. This paper briefly describes the capabilities of the LEMA AMS verification tool flow.

Type
Conference paper
Publication
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)
mixed analogue-digital integrated circuits formal verification integrated circuit design Integrated circuit modeling Delays AMS circuits digitally-intensive analog-mixed-signal circuits LEMA AMS verification tool flow property language system designs simulation trace circuit analysis clock generators voltage control voltage-controlled oscillators
Satish Batchu
Satish Batchu
Apple, Design Verification Engineer
Kevin Jones
Kevin Jones
Lockheed Martin, Senior Cyber Applied Research Scientist
Dhanashree Kulkarni
Dhanashree Kulkarni
Intel Technologies, Analog Engineer
Scott Little
Scott Little
Maxim Integrated, EDA
David Walter
David Walter
Amazon (AWS S3), Senior SDE

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