Tomohiro Yoneda | Genetic Logic Lab

Latest

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
Hazard Checking of Timed Asynchronous Circuits Revisited
Synthesis of Timed Circuits Based on Decomposition
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Symbolic Model Checking of Analog/Mixed-Signal Circuits
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
A scheduling method for asynchronous bundled-data implementations
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets
Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Verification of timed circuits with failure directed abstractions
Modular Synthesis of Timed Circuits Using Partial Order Reduction
Framework of Timed Trace Theoretic Verification Revisited
Automatic Derivation of Timing Constraints by Failure Analysis
Modular Synthesis of Timed Circuits using Partial Orders on LPNs
Framework of Timed Trace Theoretic Verification Revisited
Improved POSET timing analysis in timed Petri nets
Modular Synthesis of Timed Circuits using Partial Orders on LPNs