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T. Yoneda

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
Verification of timed circuits with failure-directed abstractions
A Scheduling Method for Asynchronous Bundled-Data Implementations Based on The Completion of Data Operations
High level synthesis of timed asynchronous circuits
Synthesis of speed independent circuits based on decomposition
Efficient verification of hazard-freedom in gate-level timed asynchronous circuits
Level oriented formal model for asynchronous circuit verification and its efficient analysis method

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