Efficient timing analysis algorithms for timed state space exploration

W. Belluomini, C.J. Myers
April 1997
DOI

Abstract

This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Much of the computational complexity in the synthesis of timed circuits currently is in finding the reachable timed state space. We introduce new algorithms which utilize geometric regions to represent the timed state space and partial orders to minimize the number of regions necessary. These algorithms operate on specifications sufficiently general to describe practical circuits.

Type
Conference paper
Publication
Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems
asynchronous circuits logic design asynchronous circuit state-space methods timed circuit synthesis timing computational complexity geometric regions timed state-space exploration partial orders timing analysis algorithms space exploration process design circuit circuit synthesis algorithm design and analysis design optimization search

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